K3502 Parking Radar... Circuit Analysis Help

Hello,

I currently using the K3502 parking radar kit on my own PCB and I’m studying how the circuit works for a college project. I am 25 years old and studying a BTEC course before starting my Degree in Electronic and Electrical Engineering, My project is important to me and I have put in a lot of hours, however I have run into a big problem with my understanding of how the circuit works which is further compounded with confusion surrounding N2 and N3 (4093)

I have been told by my tutors that N2 and N3 (Schmitt Nand Gates) form a oscillator and change the frequency to drive the piezo buzzer but I do not understand how?! they will not explain it and have asked me to do my research. I have researched Oscillators using NAND gates and they use a single NAND gate, a capacitor and resistor, they are not connected like a flip-flop…

The say they are sure, however to me it looks like N2, N3 and N5 form a latch that gives the piezo buzzer the correct polarity for it to sound (The negative leg go’s low and it sounds). While the pulse is happening TR1 turns off the receiver, when the pulse stops C3 discharges via R2 and RV1 and while there is still enough voltage at N1 the N2/N3 latch can fire, IF /RW goes low from the receiver amplifier.

So While the pulse is happening, C3 charges up via D1. After the pulse finishes, C3 discharges via RV1 and R2. Once that voltage is low enough the output on N1 will stop the N2/N3 latch operating. In other words RV1 controls the discharge time such that the slower C3 discharges the more time there is for the sensor to detect an object, meaning more time for /RW to go low. If /RW does go low before C3 is discharged the latch fires.

So am I correct in saying that N2/N3 + N5 form a Latch? or if it is a oscillator like my tutors say, how?

I tried to go to bed early tonight but its making me lose sleep and I’m wide awake.

Please help

Regards
Ray

N2,N3, N5 is a set-reset flipflop, BUZ1 has an internal oscillator.
Please Google for S-R flipflop with NAND gates theory.

Thank you